Multilayer wiring board, method for producing the same, semiconductor device and radio electronic device

ABSTRACT

A multilayer wiring board exhibiting excellent moldability and having a capacitor where variation of capacitance is suppressed, its producing method, a semiconductor device mounting a semiconductor chip on the multilayer wiring board, and a radio electronic device mounting the semiconductor device.

This application is a 371 of PCT/JP03/06860 filed May 30, 2003.

Technical Field

The present invention relates to a multilayer wiring board, amanufacturing method thereof, a semiconductor device in which asemiconductor chip is mounted on the multilayer wiring board, and awireless electronic device on which the semiconductor device is mounted.

Background Art

In recent years, with the development of electronic devices, in additionto an improvement of performance of electronic parts, the demand ofreductions in size and weight of the electronic parts becomes strict. Inparticular, in a mobile electronic device typified by a mobile phone,the demand is remarkable in pursuit of the convenience. Against such abackground, a multilayer wiring board has been used to efficiently mounta semiconductor chip or a passive device. Up to now, high-density wiringsuch as reduction in wiring line width is mainstream. However, in orderto reduce the number of parts to be mounted, passive parts typified bycapacitors are required to be built in the wiring board.

As a technique that builds a capacitor in a multilayer wiring board, atechnique that calcines a high-electric constant inorganic material toform a dielectric layer, a technique (for example, U.S. Pat. No.5,162,977) that composites a high-dielectric inorganic material and aresin material to form a dielectric layer, a technique that forms a thindielectric layer by using a process such as a sputtering process, andthe like have been known.

The technique that calcines a high-dielectric inorganic material to forma dielectric layer includes an example in which a high-dielectricmaterial suitable for simultaneous calcination of a high-dielectricmaterial and a substrate insulating material is used (see JapanesePatent Publication No. 5-55079 and Journal of Japanese Institute ofElectronics Packaging, Vol. 4, No. 2, pp. 145 to 149). The techniquethat forms a thin dielectric layer includes an example in which acapacitor is built in a resin substrate by applying a semiconductorsputter technique (see Journal of Japanese Institute of ElectronicsPackaging, Vol. 4, No. 7, pp. 590 to 596).

Since a multilayer wiring board using a technique that composites ahigh-dielectric inorganic material and a resin material to form adielectric layer does not include a high-temperature calcining step anda sputter step, the multilayer wiring board is economically excellent.Composite materials consisting of a large number of high-dielectricinorganic materials and a large number of resins are proposed to beapplied to multilayer wiring boards using resins (for example, seeJournal of Materials Science: Materials in Electronics, Vol. 11, pp. 253to 268). Methods of manufacturing capacitors in multilayer wiring boardschange depending on compositions of materials to be used. The methodsinclude a manufacturing method of a conventional multilayer wiring board(see Embedded Decoupling Capacitance Project Final Report 3-1 to 6(National Center for Manufacturing Sciences)) and a manufacturing methodof a multilayer wiring board using a high-dielectric material havingphotosensitivity (see “Integration of Thin Film Passive Circuits UsingHigh/Low Dielectric Constant Materials”, Electronic Components andTechnology Conference (1997), pp. 739 to 744).

In a multilayer wiring board in which a capacitor using a resincomposite material obtained by filling a high-dielectric filler as ahigh-dielectric material is built, when capacitors are laminated as corelayers and symmetrically arranged, both the surfaces of each core layermust be patterned. However, since the capacitor using the resincomposite material easily causes problems in breaking strength andprocessibility, both the sides of the core layer must be independentlypatterned and laminated to make the cost higher than that inmanufacturing of a conventional multilayer wiring board. In addition, inthe multilayer wiring board, when an insulating layer is used as a corelayer, high-dielectric material layers which are symmetrically laminatedwith reference to the core layer are slightly warped. However, thehigh-dielectric material layers which are asymmetrically laminated aregreatly warped. More specifically, it is very difficult to arrange acapacitor in an arbitrary layer except for a core layer to obtain amultilayer wiring board with a small warpage. Therefore, in aconventional technique, in order to solve the problem, capacitors mustbe symmetrically arranged with reference to a core layer to reduce thewarpage of a wiring board.

However, a method that symmetrically arranges and laminates capacitorsconsisting of an expensive material to reduce warpage excessivelyrequires capacitors is not economically good. Furthermore, the degree offreedom of design of a multilayer wiring board is limited.

A capacitance which is an important characteristic of a capacitor is inproportion to a specific inductive capacity, and is in inverseproportion to the thickness of a dielectric substance. Morespecifically, in order to increase the capacitance of the capacitorwithout changing the material, the thickness of the high-dielectricmaterial must be reduced. In the conventional method described in theabove documents, a high-dielectric material is decreased in thickness todeteriorate the handling properties of the material, a highmanufacturing yield cannot be achieved. In addition, like a copper foilwith adhesive agent serving as a built-up substrate material, a materialobtained by casting a high-dielectric material onto a copper foil mayalso be known. However, the filling properties and the thickness controlof an internal layer circuit pattern are posed as problems when theinternal layer pattern is laminated and integrated with an internalcircuit substrate.

A capacitance serving as an important characteristics of a capacitor isalso in proportion to the area of a counter electrode of the capacitor.More specifically, the fluctuation in area of the counter electrode mustbe reduced to suppress the fluctuation of capacitance in manufacturing.However, in formation of a capacitor electrode opposing an insulatinglayer containing a high-dielectric material, when a method that etches ametal foil covering the insulating layer in the form of a desiredpattern to form a capacitor electrode opposing an electrode formed inadvance is used, the area of the counter electrode of the capacitorchanges depending on the fluctuation of etching of the metal foil tofluctuate the capacitance of the capacitor. The fluctuation incapacitance of the capacitor caused by a shift of the counter electrodeis also posed as a problem.

Furthermore, in a multilayer wiring board for a high-frequency circuiton which a large number of passive devices are mounted, a technique thatefficiently builds inductors as passive devices except for capacitors ina substrate is also required. In the multilayer wiring board for ahigh-frequency circuit, a transmission loss is also required to bereduced.

DISCLOSURE OF THE INVENTION

According to a first aspect of the present invention, there is provideda multilayer wiring board including a plurality of insulating layers, aplurality of conductive layers, a conductive non-through hole forelectrically connecting the plurality of conductive layers to eachother, and a capacitor produced by forming electrodes on upper and lowersurfaces of at least one insulating layer containing a high-dielectricmaterial, wherein a hardened material of the high-dielectric materialhas a specific inductive capacity ranging from 20 to 100 at 25° C., 1MHz, and a thickness ranging from 0.1 to 30 μm.

In the multilayer wiring board according to the first aspect of thepresent invention, a high-dielectric material layer serving as adielectric substance of a capacitor is reduced in thickness to make itpossible to reduce the warpage of the multilayer wiring board regardlessof the symmetry or asymmetry of the layer structure. Furthermore, sincea capacitor can be built in an arbitrary layer except for a core layer,the degree of freedom of design can be largely improved. Since thenumber of capacitors may be minimum, the cost can be reduced. Since ahigh-dielectric material is reduced in thickness, the capacitance of thecapacitor which is in inverse proportion to the thickness of thedielectric material can be increased.

According to a second aspect of the present invention, there is provideda multilayer wiring board including a plurality of insulating layer, aplurality of conductive layers, a conductive non-through hole forelectrically connecting the plurality of conductive layers to eachother, and a capacitor produced by forming electrodes on upper and lowersurfaces of at least one insulating layer containing a high-dielectricmaterial, wherein an insulating material different from thehigh-dielectric material is filled in a recessed portion betweenconductive patterns including the electrodes, and the surfaces of theconductive patterns and the surface of the filled insulating materialare planarized.

In a conventional capacitor-built-in multilayer wiring board, since aninsulating resin is not filled in a recessed portion between conductivepatterns, the thickness of the high-dielectric material layer havinghigh elasticity increases in thickness. As a result, the fluctuation incapacitance of the capacitor tends to increase. In contrast to this, ina multilayer wiring board according to the second aspect of the presentinvention, the recessed portion between the conductive patterns isfilled with an insulating resin in advance as described above toplanarize the surface of the substrate on which the high-dielectricmaterial layer is to be formed. For this reason, the high-dielectriclayer can be reduced in thickness and formed with accuracy in thickness,and the fluctuation in capacitance of the capacitor can be reduced.

According to a third aspect of the present invention, there is provideda multilayer wiring board including a plurality of insulating layers, aplurality of conductive layers, a conductive hole for electricallyconnecting the conductive layers to each other, and a capacitorcomprising at least one of the insulating layers containing ahigh-dielectric material having a specific inductive capacity rangingfrom 20 to 100 at 25° C., 1 MHz and produced by forming electrodes onupper and lower surfaces of the insulating layer, wherein at least oneside of the counter electrodes has a thickness ranging from 1 to 18 μm.

In the multilayer wiring board according to the third aspect of thepresent invention, the thickness of the conductive layer is limited toimprove patterning accuracy, and the fluctuation of etching can bereduced. Furthermore, the fluctuation in capacitance, a shift ofposition, the fluctuation in size can also be suppressed.

The present invention also provides a manufacturing method of amultilayer wiring board which includes a plurality of insulating layers,a plurality of conductive layers, a conductive non-through hole forelectrically connecting the conductive layers to each other, and acapacitor produced by forming electrodes on upper and lower surfaces ofat least one insulating layer containing a high-dielectric material,including: at least the step of forming conductive patterns includingone of the electrodes; the step of filling and hardening an insulatingmaterial different from the high-dielectric material in a recessedportion between the conductive patterns; the step of planarizing thesurfaces of the conductive patterns and the surface of the insulatingmaterial filled and hardened in the recessed portion between theconductive patterns by polishing; and the step of heating and laminatinga metal foil having the high-dielectric material in a semi-hardenedstate.

The present invention still also provides a manufacturing method of amultilayer wiring board which includes a plurality of insulating layers,a plurality of conductive layers, a conductive hole for electricallyconnecting the plurality of conductive layers to each other, and acapacitor comprising at least one of the insulating layers containing ahigh-dielectric material having a specific inductive capacity rangingfrom 20 to 100 at 25° C., 1 MHz and produced by forming electrodes onupper and lower surfaces of the insulating layer, wherein, in formationof a conductive pattern, the same substrate is exposed a plurality oftimes such that a pattern exposure area of a photosensitive resist isset at 1 to 250 cm²/time.

The present invention still also provides a semiconductor device whereina semiconductor chip is mounted on the multilayer wiring board or amultilayer wiring board manufactured by the manufacturing method.

The present invention still also provides a wireless electronic devicewherein the semiconductor device is mounted.

This application claims priorities based on Japanese Patent Applicationspreviously applied by the present applicant, i.e., Japanese PatentApplications Nos. 2002-209639 (filing date: Jul. 18, 2002), 2002-209650(filing date: Jul. 18, 2002), 2002-259284 (filing date: Sep. 4, 2002),2002-259291 (filing date: Sep. 4, 2002), and 2002-324238 (filing date:Nov. 7, 2002). These specifications are incorporated in the applicationto refer to the specifications.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a sectional view showing an embodiment of a multilayer wiringboard according to the present invention.

FIG. 2 is a sectional view showing an example of a manufacturing methodof a multilayer wiring board according to the present invention.

FIG. 3 is a diagram of a wiring board showing reference symbols L, l,and h required to calculate a curvature κ.

FIG. 4 is a sectional view showing the structure of a capacitorelectrode manufactured by Example 10 and Examples 16 to 19.

FIG. 5 is a sectional view showing the structure of a capacitorelectrode manufactured by Example 11.

FIG. 6 is a sectional view showing the structure of a capacitorelectrode manufactured by Example 12.

FIG. 7 is a sectional view showing the structure of a capacitorelectrode manufactured by Example 13.

FIG. 8 is a sectional view showing the structure of a capacitorelectrode manufactured by Example 14.

FIG. 9 is a sectional view showing the structure of a capacitorelectrode manufactured by Example 15.

FIG. 10 is a sectional view showing the structure of a capacitorelectrode manufactured by Comparative Example 4.

FIG. 11 is a diagram showing minimum horizontal distances between eachside surfaces of a capacitor electrode having a thickness ranging from 1to 18 μm and each side surfaces of a capacitor electrode opposing it.

FIG. 12 is a diagram showing minimum horizontal distances between eachside surfaces of a capacitor electrode having a thickness ranging from 1to 18 μm and an outer edge of a hole formed on the electrode.

FIG. 13 is a diagram showing a portion (hatched portion) which is notconsidered as the minimum horizontal distances in FIG. 11.

BEST MODE FOR CARRYING OUT THE INVENTION

A high-dielectric material used in a capacitor of a multilayer wiringboard according to the present invention is a resin compound includingan insulating resin and a high-dielectric material filler. Theinsulating resin is not limited to a specific resin. However, as theinsulating resin, an epoxy resin which can provide a high-dielectricmaterial which can be used in a semi-hardened state and exhibitsexcellent insulating properties after hardening is preferably used.

As the epoxy resin, an epoxy resin which is hardened to achieve anadhesive function may be used. However, an epoxy resin preferablyincluding two or more functional groups and a molecular weight of lessthan 5000, more preferably, less than 3000 is used. As a bifunctionalepoxy resin, a bisphenol-A resin, a bisphenol-F resin, or the like isexemplified. The bisphenol-A liquid resin or the bisphenol-F liquidresin is commercially available as trade names: Epikote 807, Epikote827, Epikote 828, from Yuka-Shell Epoxy Co. Ltd. From Dow Chemical JapanLtd., resins are commercially available as trade names: D.E.R.330,D.E.R.331, and D.E.R.361. Furthermore, resins are commercially availableas trade names YD8125 and YDF8170 from Toto Kasei Co., Ltd.

A multifunctional epoxy resin may be added to increase aglass-transition temperature. For example, a phenol-novolac-type epoxyresin, a cresol-novolac-type epoxy resin, or the like is exemplified.The phenol-novolac-type epoxy resin is commercially available as a tradename: EPPN-201 from Nippon Kayaku co., Ltd. The cresol-novolac-typeepoxy resin is commercially available as a trade name: ESCN-190 orESCN-195 from Sumitomo Chemical Co., Ltd. The cresol-novolac-type epoxyresin is commercially available as a trade name: EOCN1025 or EOCN1027from Nippon Kayaku co., Ltd. In addition, the cresol-novolac-type epoxyresin is commercially available as a tradename: YDCN701, YDCN702,YDCN703, or YDCN704 from Toto Kasei Co., Ltd.

As a hardening agent for hardening the epoxy resin, an ordinaryhardening agent can be used. The hardening agent is not limited to aspecific hardening agent. For example, the hardening agent includesamine, polyamide, acid anhydride, polysulfide, boron trifluoride, orbisphenol A, bisphenol F, or bisphenol S serving as a compoundcontaining two or more phenolic hydroxyl groups per molecule. Inparticular, Phenol resin, such as a phenol novolac resin, a bisphenolnovolac resin, a cresol novolac resin, which is excellent in theelectric corrosion resistance at the time of moisture absorption ispreferably used. The preferable hardening agent is commerciallyavailable as a trade name: PLYOPHEN LF2882, PHENORITE TD-2090, PHENORITETD-2149, PHENORITE VH4150, and PHENORITE VH4170 from Dainippon Ink AndChemicals, Incorporated.

Furthermore, a conventionally known hardening accelerator can be usedtogether with the hardening agent. As the hardening accelerator, variousimidazoles are preferably used. The imidazoles include, for example,2-methylimidazole, 2-ethyl-4-methylimidazole,1-cyanoethyl-2-phenylimidazole,1-cyanoethyl-2-phenylimidazolium-trimellitate, and the like. Theseimidazoles are available as trade names: 2E4MZ, 2PZ-CN, and 2PZ-CNS fromShikoku Chemicals Corporation.

High-dielectric fillers include, for example, barium titanate, strontiumtitanate, calcium titanate, magnesium titanate, lead titanate, titaniumdioxide, barium zirconate, calcium zirconate, lead zirconate, and thelike. One of these high-dielectric fillers may be used, or two or moreof these high-dielectric fillers may be used. In particular, ahigh-dielectric filler having a specific inductive capacity of 50 ormore is preferably used. In addition, at least one of thehigh-dielectric fillers is preferably compounded 300 to 3000 parts byweight to an insulating resin of 100 parts by weight.

Furthermore, in order to improve the handling properties of thehigh-dielectric material used in the present invention, ahigh-molecular-weight resin having at least one functional group such asan epoxy group, an amide group, a carboxyl group, a cyanate group, or ahydroxy group and a weight-average molecular weight ranging from 10000to 800000 is preferably mixed in the high-dielectric material. Ahigh-molecular-weight resin having a weight-average molecular weight of10000 or more can reduce tack properties of the high-dielectric materialin B stage or improve flexibility in hardening. In addition, it isdifficult that the high-dielectric filler having a weight-averagemolecular weight of larger than 800000 cannot be uniformly dispersed.Such high-molecular-weight resins include, for example, a phenoxy resin,a high-molecular-weight epoxy resin, a super-high-molecular-weight epoxyresin, a polyamide-imide resin, a reactive rubber containing afunctional group, and the like. The phenoxy resin is commerciallyavailable as PHENOTOHTO YP-40 or PHENOTOHTO YP-50 from Toto Kasei Co.,Ltd. The phenoxy resin is also commercially available as a trade name:PKHC, PKHH, or PKHJ from PHENOXY ASSOCIATE Corporation. Thehigh-molecular-weight epoxy resins include a high-molecular-weight epoxyresin having a weight-average molecular weight of 30000 to 80000 and asuper-weight-average-molecular weight having a weight-average molecularweight of larger than 80000 (see Japanese Patent Publication Nos.7-59617, 7-59618, 7-59619, 7-59620, 7-64911, and 7-68327). Both theepoxy resins are manufactured in Hitachi Chemical Co., Ltd. Thepolyaimide-imide resin is commercially available as a trade name: KS9000series from Hitachi Chemical Co., Ltd. As the reactive rubber containinga functional group, an acrylic rubber containing a carboxyl group iscommercially available as a trade name: HTR-860P from Teikoku ChemicalIndustries Co., Ltd. or an acrylic rubber containing an epoxy group iscommercially available as a trade name: HTR-860P-3 from Teikoku ChemicalIndustries Co., Ltd.

Furthermore, a dispersing agent may be added to the high-dielectricmaterial used in the present invention. As a dispersing agent which canbe used, a conventional known commercial non-silicone-based dispersingagent or the like can be used. The dispersing agent is not limited to aspecific dispersing agent. In addition, a blending quantity of thedispersing agent may be appropriately determined by an experiment.

The high-dielectric material having the above-mentioned composition ismixed with an organic solvent such as methyl ethyl ketone to obtain avarnish-like solution. The solution is coated on a metal foil and driedin the form of a sheet in a B-stage state. The resultant sheet ispreferably used. Metal foils to be used here include, for example, acopper foil and an aluminum foil. The thickness of the metal foilpreferably ranges from 1 to 35 μm, more preferably ranges from 1 to 12μm. However, in a multilayer wiring board according to the third aspectof the present invention, the thickness of at least one side of a metalfoil serving as a conductive pattern including counter capacitorelectrodes is set within the range of 1 to 18 μm. The metal foil isprevented from being meal-plated to make it possible to suppress anincrease in thickness of the metal foil.

A melting viscosity of the high-dielectric material in the B-stage stateat 120° C. preferably ranges from 100 to 200 Pa·S. When the minimummelting viscosity is lower than 100 Pa·S, a fluctuation in thickness isincreased because a flow is large. When the melting viscosity is largerthan 200 Pa·S, adhesion properties are deteriorated.

In the present invention, an insulating resin used in an insulatinglayer at a position except for an insulating layer including thehigh-dielectric material is not limited to a specific insulating resin.However, as the insulating resin, an insulating resin different from thehigh-dielectric material is preferably used. Furthermore, the insulatinglayer is reinforced by a glass substrate, and an inorganic filler ispreferably added in the resin. When the insulating layer is reinforcedby the glass substrate, even though the thickness of the insulatinglayer is 150 μm or more, the insulating layer can be controlled inthickness easier than an insulating layer which is not reinforced by aglass substrate. The inorganic filler is added to reduce undulation onthe surface of the insulating layer caused by the influence of the glasssubstrate, and a multilayer wiring board having excellent high-frequencycharacteristics and a smooth surface can be obtained. As an insulatinglayer which is reinforced by a glass substrate and added with aninorganic filler, a commercial copper-clad lamination such as MCL-E-679For MCL-BE-67G (H) (trade names available from Hitachi Chemical Co.,Ltd.) or CS-3355S or CS-3357S (trade names available from RISHO KOGYOCO., LTD.) or an insulating material for interlayer adhesion such asGEA-679F or GEA-67BE (H) (trade names available from Hitachi ChemicalCo., Ltd.) or ES-3305S (trade name available from RISHO KOGYO CO.,LTD.).

The multilayer wiring board according to the present invention can alsohave an inductor together with a capacitor. The inductor is formed byetching a conductive layer, and is preferably formed on any one ofconductive patterns including the electrodes of the capacitor. Since aninductance density is high when the line width of the conductive patternis small, the conductive layer is preferably thinner than anotherconductive layer and the thickness of the conductive layer is preferablyranges from 1 to 12 μm.

The multilayer wiring board according to the present invention may havea non-through hole which simultaneously penetrates at least oneinsulating layer containing a high-dielectric material and an insulatinglayer adjacent to the insulating layer containing the high-dielectricmaterial.

The multilayer wiring board according to the present invention furtherincludes a conductive pattern having a line width of 300 μm or more onan outermost conductive layer, and the thickness of an insulating layeradjacent to the outermost conductive layer is preferably 150 μm or more.The line width is set at 300 μm or more to make it possible to suppresssignal attenuation in a high-frequency circuit, and the thickness of theinsulating layer is set at 150 μm or more to make it possible tosuppress a characteristic impedance from decreasing.

The thickness of a high-dielectric material layer in the multilayerwiring board according to the first aspect of the present inventionranges from 0.1 to 30 μm. The thickness falling in this range is alsoeffective for the multilayer wiring board according to the second andthird aspects of the present invention.

The multilayer wiring board according to the first aspect of the presentinvention can have an asymmetrical laminate structure having a capacitorformed in an arbitrary layer except for a core layer. However, in thiscase, warpage of the multilayer wiring board preferably has a curvatureof 4.0×10⁻⁴ mm⁻¹ or less, more preferably, 2.4×10⁻⁴ mm⁻¹ or less,especially preferably, 1.4×10⁻⁴ mm⁻¹ or less.

In this case, the curvature κ is the inverse number of a radius obtainedwhen a wiring board 16 as shown in FIG. 3 is regarded as a part of anarc. The curvature κ is a value calculated by the following relationalexpression (“Material System” Vol. 20 (2002), p. 131 to p. 136 edited byMaterial System and Research Laboratory, Kanazawa Institute ofTechnology) on the basis of a maximum length L and a warpage h of thewiring board:

$\kappa = \frac{8h}{{L^{2}\left( {\approx 1^{2}} \right)} + {4h^{2}}}$

It is assumed that the wiring board is warped at a constant curvatureand has equal curvatures at both the sides. The maximum length L of thewiring board represents the length of a diagonal line of the wiringboard (if the wiring board is square). In the expression 1, a directdistance 1 is used as an approximate value of the maximum length L.Furthermore, the warpage h represents a distance between a table surfaceand the bottom surface of an end of the multilayer wiring board when themultilayer wiring board is placed on the table surface to have arecessed surface facing upward, and the warpage h is preferably 1 mm orless, more preferably 0.6 mm or less, especially preferably 0.35 mm orless.

The recessed portion between the conductive patterns of the multilayerwiring board according to the second aspect of the present invention isfilled with an insulating resin to planarize a substrate surface onwhich a high-dielectric material layer is to be formed in advance. Theplanarization is also effective for the multilayer wiring boardsaccording to the first and third aspect of the present invention.

A conductive pattern including at least one electrode is preferably incontact with different insulating materials of three types including ahigh-dielectric material. More specifically, as an insulating materialfilled between the conductive patterns, a third insulating materialdifferent from the insulating resins used in the insulating layerserving as a substrate and the high-dielectric material to make itpossible to obtain a more excellent capacitor. Furthermore, a capacitoris preferably arranged in an arbitrary layer except for a core layer,and a fluctuation in capacitance of the capacitor is preferably setwithin the range of less than ±5%.

A manufacturing method of a multilayer wiring board according to thesecond aspect of the present invention includes at least the step offorming conductive patterns including one of electrodes of a capacitor,the step of filling and hardening an insulating material different froma high-dielectric material in a recessed portion between the conductivepatterns, the step of planarizing surfaces of the conductive patternsand a surface of the insulating material filed and hardened between theconductive patterns by polishing, and the step of heating and laminatinga metal foil having a high-dielectric material in a semi-hardened state.

The method includes the step of etching the metal foil to form aconductive pattern including the other of the electrodes of thecapacitor, and can further include the step of forming an inductor in atleast one of the conductor layers.

Furthermore, in the multilayer wiring board according to the thirdaspect of the present invention, as described above, the thickness of atleast one of the opposing capacitor electrodes is set within the rangeof 1 to 18 μm. However, a counter electrode area where both the opposingelectrodes overlap decreases due to a shift which can occur in patternexposure of a photosensitive resist to decrease the capacitance of thecapacitor. In order to suppress the decease in capacitance, an electrodehaving a thickness ranging from 1 to 18 μm is preferably arranged insidethe outer periphery of the electrode opposing the electrode having thethickness. More specifically, one of the electrode is made larger thanthe range in which one electrode can be shifted in the process to makeit possible to exclude a fluctuation in capacitance caused by the shiftof the electrode.

A minimum horizontal distances between each side surface of a capacitorelectrode having a thickness ranging from 1 to 18 μm and each sidesurface of the electrode opposing the capacitor electrode havingabove-mentioned thickness preferably ranges from 50 to 100 μm,respectively. When the horizontal distance is shorter than 50 μm, theprobability of decreasing a counter electrode area caused by a shift ofthe electrode increases. When the horizontal distance is longer than 100μm, the capacitor electrodes increase in size to uneconomically increasethe size of the substrate. In FIG. 11, the minimum horizontal distancebetween each side surfaces of a capacitor electrode 17 having athickness ranging from 1 to 18 μm and each side surfaces of a capacitorelectrode 18 opposing the capacitor electrode 17 is shown as a to d.However, like a hatched portion of a wiring 20 in FIG. 13, a wiringportion extending from one capacitor electrode and overlapping thecounter capacitor electrode is neglected.

A minimum horizontal distances between each side surfaces of a capacitorelectrode having a thickness ranging from 1 to 18 μm and an outer edgeof a conductive hole formed on its capacitor electrode for electricallyconnecting arbitrary conductive layers are preferably 100 μm or more,respectively. When the horizontal distance is shorter than 100 μm, theprobability of a defective connection which may be occurred by shift ofthe electrode having the thickness ranging from 1 to 18 μm and the holefor electrically connecting arbitrary conductive layers increases. InFIG. 12, A minimum horizontal distance between each side surfaces of thecapacitor electrode 17 having a thickness ranging from 1 to 18 μm andthe outer edge of a conductive hole 19, formed on the electrode, forelectrically connecting arbitrary conductive layers is shown as e to h.

The electrode having a thickness ranging from 1 to 18 μm is preferablyformed by etching and removing an unnecessary portion of a conductivelayer. As a matter of course, a capacitor according to the presentinvention can also formed by an additive method or a semi-additivemethod. However, the capacitor electrode is economically formed by asubtract method using etching, and control of a shift, a fluctuation insize and the like can also be expected according to the method.

As a manufacturing method of a multilayer wiring board according to thepresent invention, a method wherein, in formation of a conductivepattern, exposure is performed in the same substrate a plurality oftimes such that a pattern exposure area of a photosensitive resist isset at 1 to 250 cm²/time.

In particular, when a conductive pattern including the capacitorelectrode having a thickness ranging from 1 to 18 μm is formed, it ispreferable to perform the above-mentioned exposure of the plurality oftimes. When an exposure area per time is set at smaller than 1 cm², thenumber of times of exposure increases, and a manufacturing tact becomeslong to increase the cost. On the other hand, when the exposure area pertime exceeds 250 cm², a shift of a pattern cannot be easily reduced. Theexposure area per time is more preferably set within the range of 10 to200 cm², thereby easily achieve the compatibility between a reduction inshift and suppression of the manufacturing tact. Furthermore, theexposure area per time is especially preferable set within the range of50 to 150 cm². In this case, an optimum effect for the reduction inshift and the suppression of the manufacturing tact can be achieved. Inthis manner, when a divisional exposure scheme in which an exposure areaper time is reduced to perform exposure a plurality of time is used, ina large-scale substrate used in manufacturing a usual multilayer wiringboard, a shift of a conductive pattern caused in exposure can be reducedwith reference to a shift of a pattern caused by expansion andcontraction of the substrate.

In the manufacturing method, in pattern exposure of a photosensitiveresist, a photomask containing an inorganic material such as soda glassas a main component material is preferably used. In this manner, patternaccuracy after exposure and development of the photosensitive resistincreases, and the accuracy of the conductive pattern including acapacitor electrode can be improved.

The method can further include the step of etching and removing anunnecessary portion of a conductive layer to form a conductive patternincluding a capacitor electrode.

The present invention further provides a semiconductor device in which asemiconductor chip is mounted on the multilayer wiring board describedabove. When a multilayer wiring board having capacitors with a slightfluctuation in capacitance, or capacitors with a slight fluctuation incapacitance and inductors having a high inductance density in asubstrate is used to make it possible to obtain a semiconductorsubstrate which can simultaneously achieve a small size and a lightweight. A multilayer wiring board in which a conductive pattern having aline width of 300 μm or more is arranged on an outermost conductivelayer and the thickness of an insulating layer adjacent to the outermostconductive layer is 150 μm or more is used to make it possible to obtaina semiconductor device having a small high-frequency attenuation and lowreflected noise caused by characteristic impedance ununiformity.

The present invention further provides a wireless electronic device inwhich the semiconductor device is mounted. A small-size, light-weightsemiconductor device is used to achieve reductions in size and weight ofa wireless electronic device. A wireless electronic device havingexcellent high-frequency characteristics can also be obtained.

A multilayer wiring board according to the present invention and amanufacturing method of the same will be described below in detail withreference to examples. However, the present invention is not limited tothe examples.

High-Dielectric Material Sheet 1

Methyl ethyl ketone was added to a composition of matter consisting of;66 parts by weight of a bisphenol-A-type epoxy resin (YD-8125 availablefrom Toto Kasei Co., Ltd. was used) as an epoxy resin, 34 parts byweight of a cresol-novolac-type epoxy resin (YDCN-703 available fromToto Kasei Co., Ltd. was used) as an epoxy resin; 63 parts by weight ofa phenol novolac resin (PLYOPHEN LF2882 available from Dainippon Ink AndChemicals, Incorporated was used) as a hardening agent for an epoxyresin; 24 parts by weight of a phenoxy resin (weight-average molecularweight: 50000) (PHENOTOHTO YP-50 available from Toto Kasei Co., Ltd. wasused) as a high-molecular-weight resin; 0.6 parts by weight of ahardening accelerator 1-cyanoethyl-2-phenylimidazole (curezole 2PZ-CNwas used) as a hardening accelerator; 860 parts by weight of a bariumtitanate filler (BT-100PR available from Fuji Titanium Industry Co.,Ltd. was used) having an average grain diameter of 1.5 μm as ahigh-dielectric filler; and 5.4 parts by weight of a non-silicone-baseddispersing agent (BYK-W9010 available from BYK Chemie Japan KK was used)as a dispersing agent. The resultant mixture was stirred and mixed at1000 round/min for one hour by using a bead mill, filtered by 200-meshnylon cloth, and then degassed in a vacuum state. The resin varnish wascoated on an electrolytic copper foil (GTS-12 available from FURUKAWACIRCUIT FOIL Co., Ltd. was used) having a thickness of 12 μm, and washeated and dried at 140° C. for 5 minutes to form a coating film havinga thickness of 5 μm and set in a B-stage state. In this manner, ahigh-dielectric material sheet 1 including a copper foil wasmanufactured.

When a melting viscosity of the high-dielectric material sheet 1 in theB-stage state at 120° C. was measured by means of a Shimadzu flow testerModel CFT-100 (trade name available from Shimadzu Corporation) using ajig having a nozzle diameter of 2 mmφ, the melting viscosity was 100Pa·S. With respect to a hardened material hardened at 170° C. for onehour, when a dielectric constant was calculated by using an LCR meterYHP4275A (trade name available from Yokogawa Hewlett-Packard Co.,) onthe basis of an impedance characteristic at 25° C. and 1 MHz, thedielectric constant was 20.

High-Dielectric Material Sheet 2

Methyl ethyl ketone was added to a composition of matter consisting of;66 parts by weight of a bisphenol-A-type epoxy resin (YD-8125 availablefrom Toto Kasei Co., Ltd. was used) as an epoxy resin, 34 parts byweight of a cresol-novolac-type epoxy resin (YDCN-703 available fromToto Kasei Co., Ltd. was used) as an epoxy resin; 63 parts by weight ofa phenol novolac resin (PLYOPHEN LF2882 available from Dainippon Ink AndChemicals, Incorporated was used) as a hardening agent for an epoxyresin; 24 parts by weight of a polyamide-imide resin (weight-averagemolecular weight: 70000) shown by the following general formula as ahigh-molecular-weight resin;

0.6 parts by weight of a hardening accelerator1-cyanoethyl-2-phenylimidazole (curezole 2PZ-CN was used) as a hardeningaccelerator; 1300 parts by weight of a barium titanate filler (BT-100PRavailable from Fuji Titanium Industry Co., Ltd. was used) having anaverage grain diameter of 1.5 μm as a high-dielectric filler; 400 partsby weight of a barium titanate filler (HPBT-1 available from FujiTitanium Industry Co., Ltd. was used) having an average grain diameterof 0.6 μm as a high-dielectric filler; and 11.2 parts by weight of anon-silicone-based dispersing agent (BYK-W9010 available from BYK ChemieJapan KK was used) as a dispersing agent. The resultant mixture wasstirred and defoamed for one hour by using a small-size stirringdefoamer and filtered by 200-mesh nylon cloth. The resin varnish wascoated on an electrolytic copper foil (GTS-12 available from FURUKAWACIRCUIT FOIL Co., Ltd. was used) having a thickness of 12 μm, and washeated and dried at 140° C. for 5 minutes to form a coating film havinga thickness of 10 μm and set in a B-stage state. In this manner, ahigh-dielectric material sheet 2 including a copper foil wasmanufactured.

When a melting viscosity of the high-dielectric material sheet 2 in theB-stage state at 120° C. was measured by means of a Shimadzu flow testerModel CFT-100 (trade name available from Shimadzu Corporation) using ajig having a nozzle diameter of 2 mmφ, the melting viscosity was 200Pa·S. With respect to a hardened material hardened at 170° C. for onehour, when a dielectric constant was calculated by using an LCR meterYHP4275A (trade name available from Yokogawa Hewlett-Packard Co.,) onthe basis of an impedance characteristic at 25° C. and 1 MHz, thedielectric constant was 45.

High-Dielectric Material Sheet 3

Methyl ethyl ketone was added to a composition of matter consisting of;66 parts by weight of a bisphenol-A-type epoxy resin (YD-8125 availablefrom Toto Kasei Co., Ltd. was used) as an epoxy resin, 34 parts byweight of a cresol-novolac-type epoxy resin (YDCN-703 available fromToto Kasei Co., Ltd. was used) as an epoxy resin; 63 parts by weight ofa phenol novolac resin (PLYOPHEN LF2882 available from Dainippon Ink AndChemicals, Incorporated was used) as a hardening agent for an epoxyresin; 24 parts by weight of a phenoxy resin (weight-average molecularweight: 50000) (PHENOTOHTO YP-50 available from Toto Kasei Co., Ltd. wasused) as a high-molecular-weight resin; 0.6 parts by weight of ahardening accelerator 1-cyanoethyl-2-phenylimidazole (curezole 2PZ-CNwas used) as a hardening accelerator; 1300 parts by weight of a bariumtitanate filler (BT-100PR available from Fuji Titanium Industry Co.,Ltd. was used) having an average grain diameter of 1.5 μm as ahigh-dielectric filler; 400 parts by weight of a barium titanate filler(HPBT-1 available from Fuji Titanium Industry Co., Ltd. was used) havingan average grain diameter of 0.6 μm as a high-dielectric filler; and11.2 parts by weight of a non-silicone-based dispersing agent (BYK-W9010available from BYK Chemie Japan KK was used) as a dispersing agent. Theresultant mixture was stirred and mixed at 1000 round/min for one hourby using a bead mill, filtered by 200-mesh nylon cloth, and thendegassed in a vacuum state. The resin varnish was coated on anelectrolytic copper foil (GTS-12 available from FURUKAWA CIRCUIT FOILCo., Ltd. was used) having a-thickness of 12 μm, and was heated anddried at 140° C. for 5 minutes to form a coating film having a thicknessof 10 μm and set in a B-stage state. In this manner, a high-dielectricmaterial sheet 3 including a copper foil was manufactured.

When a melting viscosity of the high-dielectric material sheet 3 in theB-stage state at 120° C. was measured by means of a Shimadzu flow testerModel CFT-100 (trade name available from Shimadzu Corporation) using ajig having a nozzle diameter of 2 mmφ, the melting viscosity was 150Pa·S. With respect to a hardened material hardened at 170° C. for onehour, when a dielectric constant was calculated by using an LCR meterYHP4275A (trade name available from Yokogawa Hewlett-Packard Co.,) onthe basis of an impedance characteristic at 25° C. and 1 MHz, thedielectric constant was 45.

High-Dielectric Material Sheet 4

Methyl ethyl ketone was added to a composition of matter consisting of;66 parts by weight of a bisphenol-A-type epoxy resin (YD-8125 availablefrom Toto Kasei Co., Ltd. was used) as an epoxy resin, 34 parts byweight of a cresol-novolac-type epoxy resin (YDCN-703 available fromToto Kasei Co., Ltd. was used) as an epoxy resin; 63 parts by weight ofa phenol novolac resin (PLYOPHEN LF2882 available from Dainippon Ink AndChemicals, Incorporated was used) as a hardening agent for an epoxyresin; 24 parts by weight of a phenoxy resin (weight-average molecularweight: 50000) (PHENOTOHTO YP-50 available from Toto Kasei Co., Ltd. wasused) as a high-molecular-weight resin; 0.6 parts by weight of ahardening accelerator 1-cyanoethyl-2-phenylimidazole (curezole 2PZ-CNwas used) as a hardening accelerator; 1900 parts by weight of a bariumtitanate filler (BT-100PR available from Fuji Titanium Industry Co.,Ltd. was used) having an average grain diameter of 1.5 μm as ahigh-dielectric filler; 550 parts by weight of a barium titanate filler(HPBT-1 available from Fuji Titanium Industry Co., Ltd. was used) havingan average grain diameter of 0.6 μm as a high-dielectric filler; and15.9 parts by weight of a non-silicone-based dispersing agent (BYK-W9010available from BYK Chemie Japan KK was used) as a dispersing agent. Theresultant mixture was stirred and mixed at 1000 round/min for one hourby using a bead mill, filtered by 200-mesh nylon cloth, and thendegassed in a vacuum state. The resin varnish was coated on anelectrolytic copper foil (GTS-12 available from FURUKAWA CIRCUIT FOILCo., Ltd. was used) having a thickness of 12 μm, and was heated anddried at 140° C. for 5 minutes to form a coating film having a thicknessof 25 μm and set in a B-stage state. In this manner, a high-dielectricmaterial sheet 4 including a copper foil was manufactured.

When a melting viscosity of the high-dielectric material sheet 4 in theB-stage state at 120° C. was measured by means of a Shimadzu flow testerModel CFT-100 (trade name available from Shimadzu Corporation) using ajig having a nozzle diameter of 2 mmφ, the melting viscosity was 200Pa·S. With respect to a hardened material hardened at 170° C. for onehour, when a dielectric constant was calculated by using an LCR meterYHP4275A (trade name available from Yokogawa Hewlett-Packard Co.,) onthe basis of an impedance characteristic at 25° C. and 1 MHz, thedielectric constant was 70.

High-Dielectric Material Sheet 5

Methyl ethyl ketone was added to a composition of matter consisting of;66 parts by weight of a bisphenol-A-type epoxy resin (YD-8125 availablefrom Toto Kasei Co., Ltd. was used) as an epoxy resin, 34 parts byweight of a cresol-novolac-type epoxy resin (YDCN-703 available fromToto Kasei Co., Ltd. was used) as an epoxy resin; 63 parts by weight ofa phenol novolac resin (PLYOPHEN LF2882 available from Dainippon Ink AndChemicals, Incorporated was used) as a hardening agent for an epoxyresin; 24 parts by weight of a phenoxy resin (weight-average molecularweight: 50000) (PHENOTOHTO YP-50 available from Toto Kasei Co., Ltd. wasused) as a high-molecular-weight resin; 0.6 parts by weight of ahardening accelerator 1-cyanoethyl-2-phenylimidazole (curezole 2PZ-CNwas used) as a hardening accelerator; 860 parts by weight of a bariumtitanate filler (BT-100PR available from Fuji Titanium Industry Co.,Ltd. was used) having an average grain diameter of 1.5 μm as ahigh-dielectric filler; and 5.4 parts by weight of a non-silicone-baseddispersing agent (BYK-W9010 available from BYK Chemie Japan KK was used)as a dispersing agent. The resultant mixture was stirred and mixed at1000 round/min for one hour by using a bead mill, filtered by 200-meshnylon cloth, and then degassed in a vacuum state. The resin varnish wascoated on an electrolytic copper foil (GTS-12 available from FURUKAWACIRCUIT FOIL Co., Ltd. was used) having a thickness of 12 μm, and washeated and dried at 140° C. for 5 minutes to form a coating film havinga thickness of 30 μm and set in a B-stage state. In this manner, ahigh-dielectric material sheet 5 including a copper foil wasmanufactured.

When a melting viscosity of the high-dielectric material sheet 5 in theB-stage state at 120° C. was measured by means of a Shimadzu flow testerModel CFT-100 (trade name available from Shimadzu Corporation) using ajig having a nozzle diameter of 2 mmφ, the melting viscosity was 100Pa·S. With respect to a hardened material hardened at 170° C. for onehour, when a dielectric constant was calculated by using an LCR meterYHP4275A (trade name available from Yokogawa Hewlett-Packard Co.,) onthe basis of an impedance characteristic at 25° C. and 1 MHz, thedielectric constant was 20.

EXAMPLE 1

Desired drilling was performed to a double-side copper-plated glassepoxy laminated layer substrate MCL-E679F (trade name available fromHitachi Chemical Co., Ltd.) having a substrate thickness of 0.2 mm and asubstrate size of 500×333 cm and obtained by laminating copper foils 2each having a thickness of 3 μm on both the surfaces of a substrate 1 asshown in FIG. 2( a) (FIG. 2( b)). Carbonized resin residues were removedwith an alkali permanganic acid solution by means of ultrasoniccleaning, and catalytic addition was performed to the substrate toaccelerate adhesion. Thereafter, electroless copper plating wasperformed to form an electroless copper-plated layer 3 having athickness of about 15 μm on the inner wall of the drill hole and thesurface of the copper foil (FIG. 2( c)). Black oxide finish using sodiumhypochlorite as a main component and reduction using dimethylaminoborane as a main component were performed to the surface of thesubstrate to perform coarsening. A paste-type thermoset insulatingmaterial HRP-700BA (trade name available from Taiyo Ink Mfg Co., Ltd.) 4was filled in the drill hole of the substrate by a screen printing andhardened by heat treatment at 170° C. for 60 minutes (FIG. 2( d)). Thesubstrate surface was polished by a buff brush to remove an excessiveinsulating material. Thereafter, catalytic addition was performed to thesubstrate to accelerate adhesion. Electroless copper plating wasperformed to the substrate to form an electroless copper-plated layer 5having a thickness of about 15 μm on the substrate surface (FIG. 2( e)).After the substrate was polished by a buff brush, a photosensitive dryfilm H-9040 (trade name available from Hitachi Chemical Co., Ltd.) waslaminated on the substrate. On the substrate surface, an etching resistfor a conductive pattern including a capacitor electrode was exposed byan automatic parallel exposure system (EXM-1350B available from ORCMANUFACTURING Co., Ltd.). The substrate was developed by a sodiumcarbonate aqueous solution, and unnecessary copper was etched by ferricchloride solution. The resist was peeled by a sodium hydroxide aqueoussolution to manufacture an inner-layer circuit substrate having acircuit pattern including a lower electrode of a capacitor (FIG. 2( f))

A paste-type thermoset insulating material HRP-700BA (trade nameavailable from Taiyo Ink Mfg Co., Ltd.) 6 was coated by using a rollcoater on the surface of the inner-layer circuit substrate to have athickness of about 40 μm from the surface of the substrate insulatinglayer and a thickness of about 5 μm from the surface of the conductivepattern, and was hardened by heat treatment at 170° C. for 60 minutes.The substrate was polished by a buff brush until the surface of theconductive pattern surface was exposed to remove an excessive insulatingmaterial, thereby planarizing the inner layer circuit substrate (FIG. 2(g)). An unevenness of the surface of the inner layer circuit substratewas 3 μm or less. Thereafter, black oxide finish using sodiumhypochlorite as a main component and reduction using dimethylaminoborane as a main component were performed to the circuit surface of thecircuit substrate to perform coarsening.

A high-dielectric material sheet 1 having an insulating layer 8containing a high-dielectric material and a copper foil 7 was laminatedand integrated on one surface of the circuit substrate under pressconditions: a temperature of 170° C.; a pressure of 1.5 MPa; andheating-pressuring time of 60 minutes (FIG. 2( h)). After the laminatedstructure was polished by a buff brush, a photosensitive dry film H-9040(trade name available from Hitachi Chemical Co., Ltd.) was laminated onthe copper foil of the high-dielectric material sheet 1. On thesubstrate surface, an etching resist for a conductive pattern includinga capacitor electrode was exposed by an automatic parallel exposuresystem (EXM-1350B available from ORC MANUFACTURING Co., Ltd.). Thesubstrate was developed by a sodium carbonate aqueous solution, andunnecessary copper was etched by ferric chloride solution. The resistwas peeled by a sodium hydroxide aqueous solution to manufacture aconductive pattern including an upper electrode of the capacitor (FIG.2( i)).

Black oxide finish using sodium hypochlorite as a main component andreduction using dimethylamino borane as a main component were performedto the circuit surface of the circuit substrate to perform coarsening.(1) a copper foil MT35S3 (trade name available from Mitsui Mining AndSmelting Company, Limited) 9, (2) two sheets of filler-contained glassepoxy prepreg GEA-679F (trade name available from Hitachi Chemical Co.,Ltd.) 10 each having a thickness of 80 μm, (3) the circuit substrate inFIG. 2( i), (4) two sheets of filler-contained glass epoxy prepregGEA-679F each having a thickness of 80 μm, (5) a copper foil MT35S3(trade name available from Mitsui Mining And Smelting Company, Limited)whose thickness is 3 μm and having a 35 μm carrier copper foil werelaminated in the order named, and laminated and integrated under pressconditions: a temperature of 170° C.; a pressure of 1.5 MPa; andheating-pressuring time of 60 minutes (FIG. 2( j)). The carrier copperfoil was peeled, and an unnecessary substrate end was cut out.Thereafter, a desired etching resist was formed on the surface of thesubstrate, and an unnecessary copper foil was etched by using a ferricchloride aqueous solution to form a window hole having a diameter ofφ0.15 mm at a desired position.

At the position corresponding to the window hole formed in the substratesurface, laser boring was performed by using a Model ML505GT carbondioxide laser available from Mitsubishi Electric Corporation underconditions: output power of 26 mJ, pulse width of 10 μs, and six shots(FIG. 2( k)). After carbonized resin residues were removed with analkali permanganic acid solution by means of ultrasonic cleaning,cleaning and catalytic addition were performed to the substrate toaccelerate adhesion. Thereafter, electroless copper plating wasperformed by using CUST-3000 (trade name available from Hitachi ChemicalCo., Ltd.) to form an electroless copper-plated layer 11 having athickness of about 20 μm on the inner wall of the laser hole and thesurface of the copper foil (FIG. 2( l)). An etching resist was formed atnecessary portions such as pads on the substrate surface, the circuitpattern, and the like, and unnecessary copper was etched by using aferric chloride aqueous solution to form an outer layer circuit (FIG. 2(m)).

A solder resist PSR-4000AUS5 (trade name available from Taiyo Ink MfgCo., Ltd.) was coated by using a roll coater on the substrate surface tohave a thickness of 30 μm and dried, and then exposed and developed toform a solder resist 15 at a desired position. Thereafter, on thesurface layer of the exposed part of an outer layer circuit pattern, anelectroless nickel-plated layer 13 with a thickness of 3 μm is formedusing NIPS100 (trade name available from Hitachi Chemical Co., Ltd.) andan electroless gold-plated layer 14 with a thickness of 0.1 μm is formedusing HGS2000 (trade name Hitachi Chemical Co., Ltd.) to obtain afive-layer multilayer wiring board in which a capacitor 12 as shown inFIG. 1 was built.

EXAMPLE 2

A multilayer wiring board was obtained by the same steps as those inExample 1 except that the high-dielectric material sheet 2 was used inplace of the high-dielectric material sheet 1.

EXAMPLE 3

A multilayer wiring board was obtained by the same steps as those inExample 1 except that the high-dielectric material sheet 3 was used inplace of the high-dielectric material sheet 1.

EXAMPLE 4

A multilayer wiring board was obtained by the same steps as those inExample 1 except that the high-dielectric material sheet 4 was used inplace of the high-dielectric material sheet 1.

EXAMPLE 5

A multilayer wiring board was obtained by the same steps as those inExample 1 except that an inner layer circuit substrate was notplanarized by resin filling as shown in FIG. 2( g) and that thehigh-dielectric material sheet 5 was used in place of thehigh-dielectric material sheet 1.

COMPARATIVE EXAMPLE 1

A multilayer wiring board was obtained by the same steps as those inExample 5 except that a copper foil MCF6000E (trade name available fromHitachi Chemical Co., Ltd.) with an epoxy-based resin whose thickness ofdielectric-material layer is 80 μm was used as a high-dielectricmaterial sheet.

Each of the multilayer wiring boards obtained by Examples 1 to 5 andComparative Example 1 was cut into pieces to obtain test samples eachhaving a size of 100 mm×100 mm, and warpages of the samples weremeasured. Furthermore, curvatures were calculated by using theexpression 1. The obtained results were shown in Table 1.

TABLE 1 Thickness of High-dielectric Warpage Curvature Item MaterialLayer (μm) (mm) (mm⁻¹) Example 1 5 0.3 1.20 × 10⁻⁴ Example 2 10 0.4 1.60× 10⁻⁴ Example 3 10 0.4 1.60 × 10⁻⁴ Example 4 25 0.5 2.00 × 10⁻⁴ Example5 30 0.7 2.80 × 10⁻⁴ Comparative 80 1.2 4.80 × 10⁻⁴ Example 1

Each of the multilayer wiring boards according to Example 1 to 5 is acapacitor-built-in multilayer wiring board in which a specific inductivecapacity of a high-dielectric hardened material ranges 20 to 100 at 25°C., 1 MHz and which has a thickness of 0.1 to 30 μm. All the multilayerwiring boards according to Example 1 to 5 have a curvature of4.0×10⁻⁴mm⁻¹ or less and a small warpage of 1 mm or less. On the otherhand, in Comparative Example 1, since the thickness of thehigh-dielectric material is 80 μm, the curvature of the high-dielectricmaterial exceeds 4.0×10⁻⁴ mm⁻¹, and a warpage also exceeds 1 mm.

EXAMPLE 6

With respect to the multilayer wiring board obtained in Example 1, afluctuation in capacitance of a capacitor and moldability wereevaluated. A method of measuring a capacitance of capacitor and a methodof evaluating moldability are as follows.

(Capacitance of Capacitor)

In measurement of a capacitance of a capacitor, a measurement systemobtained by connecting a high-frequency signal measurement probeMICROPROBE ACP50 (Model GSG250, trade name available from CascadeCorporation) to an impedance analyzer 4291B (trade name available fromAgilent Technologies) through a 50, coaxial cable SUCOFLEX104/100 (tradename available SUHNER INC.) was used. The electrode size of thecapacitor was set at 1 mm×1 mm to measure a capacitance at 1 GHz.Capacitances of capacitors arranged at five portions, i.e., the fourcorners and the center of the substrate were measured.

(Moldability)

The moldability was evaluated whether voids and the like are in themultilayer wiring board after cutting the manufactured multilayer wiringboard in a size of 10 mm×30 mm, casting an epoxy resin and polishing thecross-section of the substrate. When no voids or the like were present,it was determined that the moldability was good. When voids or the likewere present, it was determined that the moldability was not good.

EXAMPLE 7

With respect to a multilayer wiring board obtained in Example 2, afluctuation in capacitance of a capacitor and moldability were evaluatedas in the same manner as that in Example 6.

EXAMPLE 8

With respect to a multilayer wiring board obtained in Example 3, afluctuation in capacitance of a capacitor and moldability were evaluatedas in the same manner as that in Example 6.

EXAMPLE 9

With respect to a multilayer wiring board obtained in Example 4, afluctuation in capacitance of a capacitor and moldability were evaluatedin the same manner as that in Example 6.

COMPARATIVE EXAMPLE 2

With respect to a multilayer wiring board which was manufactured in thesame manner as that in Example 3 except that an inner layer circuitsubstrate was not planarized by filling a resin as shown in FIG. 2( g),a fluctuation in capacitance of a capacitor and moldability wereevaluated in the same manner as that in Example 6.

COMPARATIVE EXAMPLE 3

With respect to the multilayer wiring board obtained in Example 5, afluctuation in capacitance of a capacitor and moldability were evaluatedin the same manner as that in Example 6.

Results obtained in Examples 6 to 9 and Comparative Examples 2 and 3 areshown in Table 2.

TABLE 2 Capacitance of Capacitor (pF) Maximum Minimum Average Item ValueValue Value Moldability Example 6 31 32 32 Good 7 37 35 36 Good 8 38 3536 Good 9 23 22 23 Good Comparative 2 39 36 38 Not good Example 3 36 3032 Good

In each of Examples 6 to 9, a third thermoset insulating material whichis different in a substrate material and a high-dielectric material wasfilled in a recessed portion between capacitor electrodes and wasplanarized. For this reason, a fluctuation in capacitance of a capacitorwas small, i.e., less than ±5%, and the moldability was good. On theother hand, in Comparative Example 2, the moldability was not goodbecause voids were present between the capacitor electrodes. InComparative Example 3, the fluctuation in capacitance of the capacitorexceeded 10%. On the basis of a result of cross-section observation, itwas understood that the large fluctuation was because the thickness ofan insulating layer containing a high-dielectric material largelyfluctuated within the range of 3 to 6 μm.

Multilayer wiring boards using the following high-dielectric materialsheets 6 to 10 were manufactured as the following Examples 10 to 19 andComparative Example 4. shift of capacitor electrodes, fluctuations insize, and fluctuations in capacitance, on these multilayer wiring boardswere evaluated.

High-Dielectric Material Sheet 6

Methyl ethyl ketone was added to a composition of matter consisting of;66 parts by weight of a bisphenol-A-type epoxy resin (YD-8125 availablefrom Toto Kasei Co., Ltd. was used) as an epoxy resin, 34 parts byweight of a cresol-novolac-type epoxy resin (YDCN-703 available fromToto Kasei Co., Ltd. was used) as an epoxy resin; 63 parts by weight ofa phenol novolac resin (PLYOPHEN LF2882 available from Dainippon Ink AndChemicals, Incorporated was used) as a hardening agent for an epoxyresin; 24 parts by weight of a phenoxy resin (weight-average molecularweight: 50000) (PHENOTOHTO YP-50 available from Toto Kasei Co., Ltd. wasused) as a high-molecular-weight resin; 0.6 parts by weight of ahardening accelerator 1-cyanoethyl-2-phenylimidazole (curezole 2PZ-CNwas used) as a hardening accelerator; 1300 parts by weight of a bariumtitanate filler (BT-100PR available from Fuji Titanium Industry Co.,Ltd. was used) having an average grain diameter of 1.5 μm as ahigh-dielectric filler; 400 parts by weight of a barium titanate filler(HPBT-1 available from Fuji Titanium Industry Co., Ltd. was used) havingan average grain diameter of 0.6 μm as a high-dielectric filler; and11.2 parts by weight of a non-silicone-based dispersing agent (BYK-W9010available from BYK Chemie Japan KK was used) as a dispersing agent. Theresultant mixture was stirred and mixed at 1000 round/min for one hourby using a bead mill, filtered by 200-mesh nylon cloth, and thendegassed in a vacuum state. The resin varnish was coated on anelectrolytic copper foil (GTS-12 available from FURUKAWA CIRCUIT FOILCo., Ltd. was used) having a thickness of 12 μm, and was heated anddried at 140° C. for 5 minutes to form a coating film having a thicknessof 10 μm and set in a B-stage state. In this manner, a high-dielectricmaterial sheet 6.

With respect to a hardened material obtained by hardening the B-stageadhesive film at 170° C. for one hour, when a dielectric constant wascalculated by using an LCR meter YHP4275A (trade name available fromYokogawa Hewlett-Packard Co.,) on the basis of an impedancecharacteristic at 25° C. and 1 MHz, the dielectric constant was 45.

High-Dielectric Material Sheet 7

A high-dielectric material sheet 7 was obtained by the same steps asthose of the high-dielectric material sheet 6 except that theelectrolytic copper foil to be coated with the adhesive varnish wasreplaced with a copper foil (MT35S3 available from Mitsui Mining AndSmelting Company, Limited was used) whose thickness is 3 μm and having a35 μm carrier copper foil.

With respect to a hardened material obtained by hardening the B-stageadhesive film at 170° C. for one hour, when a dielectric constant wascalculated by using an LCR meter YHP4275A (trade name available fromYokogawa Hewlett-Packard Co.,) on the basis of an impedancecharacteristic at 25° C. and 1 MHz, the dielectric constant was 45.

High-Dielectric Material Sheet 8

A high-dielectric material sheet 8 was obtained by the same steps asthose of the high-dielectric material sheet 6 except that theelectrolytic copper foil to be coated with the adhesive varnish wasreplaced with an electrolytic copper foil (GTS-9 available from FURUKAWACIRCUIT FOIL Co., Ltd. was used) having a thickness of 9 μm.

With respect to a hardened material obtained by hardening the B-stageadhesive film at 170° C. for one hour, when a dielectric constant wascalculated by using an LCR meter YHP4275A (trade name available fromYokogawa Hewlett-Packard Co.,) on the basis of an impedancecharacteristic at 25° C. and 1 MHz, the dielectric constant was 45.

High-Dielectric Material Sheet 9

A high-dielectric material sheet 9 was obtained by the same steps asthose of the high-dielectric material sheet 6 except that theelectrolytic copper foil to be coated with the adhesive varnish wasreplaced with an electrolytic copper foil (GTS-18 available fromFURUKAWA CIRCUIT FOIL Co., Ltd. was used) having a thickness of 18 μm.

With respect to a hardened material obtained by hardening the B-stageadhesive film at 170° C. for one hour, when a dielectric constant wascalculated by using an LCR meter YHP4275A (trade name available fromYokogawa Hewlett-Packard Co.,) on the basis of an impedancecharacteristic at 25° C. and 1 MHz, the dielectric constant was 45.

High-Dielectric Material Sheet 10

A high-dielectric material sheet 10 was obtained by the same steps asthose of the high-dielectric material sheet 6 except that theelectrolytic copper foil to be coated with the adhesive varnish wasreplaced with an electrolytic copper foil (GTS-35 available fromFURUKAWA CIRCUIT FOIL Co., Ltd. was used) having a thickness of 35 μm.

With respect to a hardened material obtained by hardening the B-stageadhesive film at 170° C. for one hour, when a dielectric constant wascalculated by using an LCR meter YHP4275A (trade name available fromYokogawa Hewlett-Packard Co.,) on the basis of an impedancecharacteristic at 25° C. and 1 MHz, the dielectric constant was 45.

EXAMPLE 10

A multilayer wiring board was obtained in the same manner as that inExample 1 except that the high-dielectric material sheet 6 was used inplace of the high-dielectric material sheet 1, that exposure information of the upper electrode of the capacitor was performed by usinga divisional projection exposure system Model UX-5038SC available fromUSHIO INC. in place of an automatic parallel exposure system ModelEXM-1350B available from ORC MANUFACTURING Co., Ltd. such that the sheetwas divided into patterns each having an area of 10 cm square by using aphotomask containing soda glass as a base material, and that the upperand lower electrodes of the capacitor were formed to have sizes of 1.0mm×0.75 mm, respectively. The sectional view of a capacitor 12 inExample 10 is shown in FIG. 4.

EXAMPLE 11

A multilayer wiring board was obtained in the same manner as that inExample 10 except that the sizes of the upper and lower electrodes ofthe capacitors were 1.0 mm×0.75 mm and 1.05×0.755 mm, respectively. Thesectional view of a capacitor 12 in Example 11 is shown in FIG. 5.

EXAMPLE 12

A multilayer wiring board was obtained in the same manner as that inExample 10 except that the sizes of the upper and lower electrodes ofthe capacitors were 1.0 mm×0.75 mm and 1.1×0.85 mm, respectively. Thesectional view of a capacitor 12 in Example 12 is shown in FIG. 6.

EXAMPLE 13

A multilayer wiring board was obtained in the same manner as that inExample 10 except that the sizes of the upper and lower electrodes ofthe capacitors were 1.0 mm×0.75 mm and 1.2×0.95 mm, respectively. Thesectional view of a capacitor 12 in Example 13 is shown in FIG. 7.

EXAMPLE 14

A multilayer wiring board was obtained in the same manner as that inExample 10 except that the sizes of the upper and lower electrodes ofthe capacitors were 1.0 mm×0.75 mm and 1.4×1.15 mm, respectively. Thesectional view of a capacitor 12 in Example 14 is shown in FIG. 8.

EXAMPLE 15

A multilayer wiring board was obtained in the same manner as that inExample 10 except that the high-dielectric material sheet 7 was used inplace of the high-dielectric material sheet 6, that an upper electrodeof a capacitor was formed by forming an electrolytic copper-plated layerhaving a thickness of about 15 μm on the copper foil of thehigh-dielectric material sheet 7 and etching an underlying copper by aliquid mixture of sulfuric acid and hydrogen peroxide after a platingresist was peeled, and that the sizes of the upper and lower electrodesof the capacitors were 1.0 mm×0.75 mm and 1.1×0.85 mm, respectively. Thesectional view of a capacitor 12 in Example 15 is shown in FIG. 9.

EXAMPLE 16

A multilayer wiring board was obtained in the same manner as that inExample 10 except that exposure was performed such that the sheet wasdivided into patterns each having an area of 5 cm square in use of adivisional projection exposure system. The sectional view of a capacitor12 in Example 16 is shown in FIG. 4.

EXAMPLE 17

A multilayer wiring board was obtained in the same manner as that inExample 10 except that exposure was performed such that the sheet wasdivided into patterns each having an area of 15 cm square in use of adivisional projection exposure system. The sectional view of a capacitor12 in Example 17 is shown in FIG. 4.

EXAMPLE 18

A multilayer wiring board was obtained in the same manner as that inExample 10 except that the high-dielectric material sheet 8 was used inplace of the high-dielectric material sheet 6. The sectional view of acapacitor 12 in Example 18 is shown in FIG. 4.

EXAMPLE 19

A multilayer wiring board was obtained in the same manner as that inExample 10 except that the high-dielectric material sheet 9 was used inplace of the high-dielectric material sheet 6. The sectional view of acapacitor 12 in Example 19 is shown in FIG. 4.

COMPARATIVE EXAMPLE 4

A multilayer wiring board was obtained in the same manner as that inExample 10 except that the high-dielectric material sheet 10 was used inplace of the high-dielectric material sheet 6, that exposure information of the upper electrode of the capacitor was performed by batchexposure using an automatic parallel exposure system Model EXM-1350Bavailable from ORC MANUFACTURING Co., Ltd. in place of a divisionalprojection exposure system Model UX-5038SC available from USHIO INC.using a photomask containing polyester as a base material. The sectionalview of a capacitor 12 in Comparative Example 4 is shown in FIG. 10.

With respect to the multilayer wiring boards manufactured as describedabove, capacitor portions were cut out and cast with an epoxy resin, andsubstrate cross sections were polished. Shifts between counterelectrodes of the capacitors and the area of the upper electrode of thecapacitor were measured from the cross sections using a microscope witha scale (MX50 available from OLYMPUS Co., Ltd.). The number ofmeasurement samples of each multilayer wiring board is 12 samples. Themeasurement results are shown in Table 3 and Table 4.

TABLE 3 Shift of Counter Electrode (μm) Item Maximum Minimum AverageExample 10 39.4 2.2 13.1 16 27.2 5.3 10.8 17 40.8 7.0 16.4 ComparativeExample 4 82.4 14.4 40.2

TABLE 4 Area of Upper Electrode (mm²) Item Maximum Minimum AverageFluctuation (%) Example 10 0.756 0.743 0.747 ±0.9 18 0.755 0.743 0.749±0.8 19 0.760 0.742 0.751 ±1.2 Comparative 0.771 0.733 0.754 ±2.6Example 4

In Table 3, although shifts between the counter electrodes were lessthan 50 μm in Examples 10, 16, and 17, a shift between the counterelectrodes was 80 μm or more in Comparative Example 4. In Table 4,although fluctuations of the upper electrodes were about ±1% in Examples10, 18, and 19, a fluctuation of the upper was large, i.e., ±2.6% inComparative Example 4. These results were obtained because thethicknesses of the capacitor electrodes were made thin in manufacture ofthe multilayer wiring boards of Examples 10 to 19 to reduce fluctuationsin etching and because exposure was performed by a divisional exposurescheme using glass-based high-precision photomasks to form conductivepatterns in manufacture of the multilayer wiring boards of Examples 10to 19.

Fluctuations in capacitance of capacitors were calculated bycalculations using the results in Table 3 and Table 4. The results areshown in Table 5.

TABLE 5 Capacitance of Capacitor (pF) Item Maximum Minimum AverageFluctuation (%) Example 10 15.02 14.15 14.84 ±3.01 11 15.09 14.69 14.92±1.44 12 15.12 14.85 14.94 ±0.89 13 15.13 14.87 15.01 ±0.99 14 15.1214.86 14.99 ±0.89 15 15.10 14.84 14.97 ±0.87 16 15.04 14.16 14.60 ±2.7817 15.00 14.08 14.44 ±3.43 18 15.00 14.16 14.58 ±2.88 19 14.99 13.9814.49 ±3.49 Comparative Example 14.89 12.46 13.80 ±8.82

As is apparent from Table 5, the fluctuations in capacitance of thecapacitors in Examples 10 to 19 are smaller than the fluctuation inComparative Example 4. Since no significant differences can be observedin Examples 12 to 14, it is understood that, in consideration offluctuations in position in exposure of photosensitive resists, occupiedareas of the capacitors can be small by designing the areas of the lowerelectrodes to the minimum and it is preferably. Since no significantdifference can be observed in comparison between Example 12 using thesubtract method and Example 15 using the semi-additive method, it isunderstood that a conductive pattern including a capacitor electrode canbe preferably formed by the subtract method having an economicaladvantage.

As described above, according to the multilayer wiring board of thepresent invention, a high-dielectric material layer serving as adielectric portion of a capacitor is reduced in thickness to make itpossible to reduce warpage of the multilayer wiring board regardless ofsymmetry or asymmetry of a layer structure. Furthermore, since acapacitor can be built in an arbitrary layer except for a core layer,the degree of freedom of design can be considerably improved. Since thenumber of capacitors can be suppressed to the minimum number, the costcan be reduced. Since the high-dielectric material has a smallthickness, a capacitance of capacitor which is in inverse proportion tothe thickness of the dielectric can be increased.

A multilayer wiring board including a thin high-dielectric material, acapacitor having a small fluctuation in capacitance and no problem inmoldability, and a manufacturing method of the same can be provided.

A semiconductor device in which a semiconductor chip is mounted on themultilayer wiring board having the above characteristic features and awireless electronic device on which the semiconductor device is mountedcan be provided.

It will be apparent to persons skilled in the art that the above is apreferable embodiment of the invention and that various changes andmodifications can be executed without departing from the spirit andscope of the invention.

1. A multilayer wiring board comprising a plurality of insulatinglayers, a plurality of conductive layers, a conductive non-through holefor electrically connecting the plurality of conductive layers to eachother, and a capacitor produced by forming electrodes on upper and lowersurfaces of at least one insulating layer containing a high-dielectricmaterial, wherein the capacitor is in an arbitrary layer except for acore layer and a layer structure is asymmetrical, a warpage is4.0×10⁻⁴mm⁻¹ or less in curvature at a room temperature, and a hardenedmaterial of the high-dielectric material has a specific inductivecapacity ranging from 20 to 100 at 25° C., 1 MHz and a thickness rangingfrom 0.1 to 30 μm.
 2. The multilayer wiring board according to claim 1,wherein the capacitor is in an arbitrary layer except for a core layerand a layer structure is asymmetrical, and a warpage is 1 mm or less. 3.A multilayer wiring board comprising a plurality of insulating layers, aplurality of conductive layers, a conductive non-through hole forelectrically connecting the plurality of conductive layers to eachother, and a capacitor produced by forming electrodes on upper and lowersurfaces of at least one insulating layer containing a high-dielectricmaterial, wherein an insulating material different from thehigh-dielectric material is filled in a recessed portion betweenconductive patterns including the electrodes, and the surfaces of theconductive patterns and the surface of the filled insulating materialare planarized.
 4. The multilayer wiring board according to claim 3,wherein the conductive pattern including at least one of the electrodesis in contact with different insulating materials of three typesincluding the high-dielectric material.
 5. A multilayer wiring boardcomprising a plurality of insulating layers, a plurality of conductivelayers, a conductive hole for electrically connecting the plurality ofconductive layers to each other, and a capacitor comprising at least oneof the insulating layers containing a high-dielectric material having aspecific inductive capacity ranging from 20 to 100 at 25° C., 1 MHz andproduced by forming electrodes on upper and lower surfaces of theinsulating layer, wherein at least one side of the counter electrodeshas a thickness ranging from 1 to 18 μm and is arranged inside an outerperiphery of the electrode opposing the electrode having the thickness.6. The multilayer wiring board according to claim 5, wherein a minimumhorizontal distance between each side surface of the electrode havingthe thickness ranging from 1 to 18 μm and each side surface of theelectrode opposing it are respectively ranging from 50 to 100 μm.
 7. Themultilayer wiring board according to claim 5, wherein a minimumhorizontal distance between each side surface of the electrode havingthe thickness ranging from 1 to 18 μm and an outer edge of theconductive hole formed on the electrode for electrically connectingarbitrary conductive layers are respectively 100 μm or more.
 8. Themultilayer wiring board according to claim 5, wherein the electrodehaving the thickness ranging from 1 to 18 μm is formed by etching andremoving an unnecessary portion of a conductive layer.
 9. The multilayerwiring board according to claim 3, wherein the capacitor is in anarbitrary layer except for a core layer, and a fluctuation incapacitance of the capacitor is less than ±5%.
 10. The multilayer wiringboard according to claim 1, comprising an inductor formed by patterningat least one conductive layer.
 11. The multilayer wiring board accordingto claim 10, wherein a thickness of the conductive layer in which theinductor is formed is smaller than a thickness of another conductivelayer and ranges from 1 to 12 μm.
 12. The multilayer wiring boardaccording to claim 10, wherein the inductor is manufactured on any oneof the electrodes formed on the upper and lower surfaces of theinsulating layer.
 13. The multilayer wiring board according to claim 1,comprising a non-through hole which simultaneously penetrates at leastone of the insulating layer containing the high-dielectric material andanother insulating layer adjacent to the insulating layer containing thehigh-dielectric material.
 14. The multilayer wiring board according toclaim 1, wherein the high-dielectric material contains an epoxy resin, ahardening agent for the epoxy resin, and a high-dielectric materialfiller.
 15. The multilayer wiring board according to claim 1, whereinthe high-dielectric material contains an epoxy resin, a hardening agentfor the epoxy resin, a high-dielectric material filler, and ahigh-molecular-weight resin having at least one functional group and aweight-average molecular weight ranging from 10000 to
 800000. 16. Themultilayer wiring board according to claim 1, wherein a meltingviscosity of the high-dielectric material in a B-stage state at 120° C.preferably ranges from 100 to 200 Pa·S.
 17. The multilayer wiring boardaccording to claim 14, wherein the high-dielectric material filler is atleast one selected from the group consisting of barium titanate,strontium titanate, calcium titanate, magnesium titanate, lead titanate,titanium dioxide, barium zirconate, and calcium zirconate, leadzirconate.
 18. The multilayer wiring board according to claim 14,wherein the high-dielectric filler is compounded 300 to 3000 parts byweight to the epoxy resin of 100 parts by weight.
 19. The multilayerwiring board according to claim 1, wherein, as an outermost conductivelayer, at least one conductive pattern having a width of 300 μm or moreis formed, and a thickness of an insulating layer adjacent to theoutermost conductive layer is 150 μm or more.
 20. The multilayer wiringboard according to claim 1, wherein an insulating layer except for atleast one of the insulating layers containing the high-dielectricmaterial is reinforced by a glass substrate and contains an inorganicfiller.
 21. The multilayer wiring board according to claim 1, whereinthe electrodes formed on the upper and lower surfaces of the insulatinglayer are formed so that one surface or both the surfaces of theinsulating layer may not be entirely covered.
 22. A semiconductor devicewherein a semiconductor chip is mounted on a multilayer wiring boardaccording to claim
 1. 23. A wireless electronic device wherein asemiconductor device according to claim 22 is mounted.
 24. Themultilayer wiring board according to claim 6, wherein a minimumhorizontal distance between each side surface of the electrode havingthe thickness ranging from 1 to 18 μm and an outer edge of theconductive hole formed on the electrode for electrically connectingarbitrary conductive layers are respectively 100 μm or more.
 25. Themultilayer wiring board according to claim 6, wherein the electrodehaving the thickness ranging from 1 to 18 μm is formed by etching andremoving an unnecessary portion of a conductive layer.
 26. Themultilayer wiring board according to claim 7, wherein the electrodehaving the thickness ranging from 1 to 18 μm is formed by etching andremoving an unnecessary portion of a conductive layer.
 27. Themultilayer wiring board according to claim 5, wherein the capacitor isin an arbitrary layer except for a core layer, and a fluctuation incapacitance of the capacitor is less than ±5%.
 28. The multilayer wiringboard according to claim 3, comprising an inductor formed by patterningat least one conductive layer.
 29. The multilayer wiring board accordingto claim 5, comprising an inductor formed by patterning at least oneconductive layer.
 30. The multilayer wiring board according to claim 3,comprising a non-through hole which simultaneously penetrates at leastone of the insulating layer containing the high-dielectric material andanother insulating layer adjacent to the insulating layer containing thehigh-dielectric material.
 31. The multilayer wiring board according toclaim 5, comprising a non-through hole which simultaneously penetratesat least one of the insulating layer containing the high-dielectricmaterial and another insulating layer adjacent to the insulating layercontaining the high-dielectric material.
 32. The multilayer wiring boardaccording to claim 3, wherein the high-dielectric material contains anepoxy resin, a hardening agent for the epoxy resin, and ahigh-dielectric material filler.
 33. The multilayer wiring boardaccording to claim 5, wherein the high-dielectric material contains anepoxy resin, a hardening agent for the epoxy resin, and ahigh-dielectric material filler.
 34. The multilayer wiring boardaccording to claim 3, wherein the high-dielectric material contains anepoxy resin, a hardening agent for the epoxy resin, a high-dielectricmaterial filler, and a high-molecular-weight resin having at least onefunctional group and a weight-average molecular weight ranging from10000 to
 800000. 35. The multilayer wiring board according to claim 5,wherein the high-dielectric material contains an epoxy resin, ahardening agent for the epoxy resin, a high-dielectric material filler,and a high-molecular-weight resin having at least one functional groupand a weight-average molecular weight ranging from 10000 to
 800000. 36.The multilayer wiring board according to claim 3, wherein a meltingviscosity of the high-dielectric material in a B-stage state at 120° C.preferably ranges from 100 to 200 Pa·S.
 37. The multilayer wiring boardaccording to claim 5, wherein a melting viscosity of the high-dielectricmaterial in a B-stage state at 120° C. preferably ranges from 100 to 200Pa·S.
 38. The multilayer wiring board according to claim 3, wherein, asan outermost conductive layer, at least one conductive pattern having awidth of 300 μm or more is formed, and a thickness of an insulatinglayer adjacent to the outermost conductive layer is 150 μm or more. 39.The multilayer wiring board according to claim 5, wherein, as anoutermost conductive layer, at least one conductive pattern having awidth of 300 μm or more is formed, and a thickness of an insulatinglayer adjacent to the outermost conductive layer is 150 μm or more. 40.The multilayer wiring board according to claim 3, wherein an insulatinglayer except for at least one of the insulating layers containing thehigh-dielectric material is reinforced by a glass substrate and containsan inorganic filler.
 41. The multilayer wiring board according to claim5, wherein an insulating layer except for at least one of the insulatinglayers containing the high-dielectric material is reinforced by a glasssubstrate and contains an inorganic filler.
 42. The multilayer wiringboard according to claim 3, wherein the electrodes formed on the upperand lower surfaces of the insulating layer are formed so that onesurface or both the surfaces of the insulating layer may not be entirelycovered.
 43. The multilayer wiring board according to claim 5, whereinthe electrodes formed on the upper and lower surfaces of the insulatinglayer are formed so that one surface or both the surfaces of theinsulating layer may not be entirely covered.
 44. A semiconductor devicewherein a semiconductor chip is mounted on a multilayer wiring boardaccording to claim
 3. 45. A wireless electronic device wherein asemiconductor device according to claim 44 is mounted.
 46. Asemiconductor device wherein a semiconductor chip is mounted on amultilayer wiring board according to claim
 5. 47. A wireless electronicdevice wherein a semiconductor device according to claim 46 is mounted.